Chip startup says an AI system designed and verified a chip in two weeks
Architect Labs, a Palo Alto startup, reported figures against Nvidia's Jetson Orin Nano that have not been independently verified; the design was deployed on an FPGA, not fabricated silicon.
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Architect Labs, a Palo Alto startup that raised $24 million in seed funding in June 2026, reported that an AI system it built designed, verified and deployed a complete AI accelerator chip, which it calls Redwood, from a human-written specification in under two weeks with no human intervention below that specification.
According to the company’s own account, published as both an arXiv paper and a company blog post, the system generated the accelerator’s performance model, its RTL (the hardware description defining the chip’s logic), verification environments, formal proofs, firmware and compute kernels — collapsing into one automated process steps that conventionally involve separate specialist teams and stages of manual verification. The chip is a tile-based design aimed at low-power, low-latency inference for “physical AI” workloads such as robotics, and the company said it has run open-weight models including Llama and Qwen on it.
[T]he system autonomously generated the performance model, RTL design, UVM environments, formal proofs, firmware, and kernels in under two weeks with no human intervention below the specification.
The company reported that, projected onto Samsung’s 8-nanometre manufacturing process — the same process class used by Nvidia’s Jetson Orin Nano, an existing edge-AI chip — Redwood would deliver 1.75 times the throughput at 1.9 times lower power. That comparison is a projection rather than a measurement of fabricated silicon: Redwood currently exists only as a design running on FPGA hardware, used to test a chip’s logic before committing it to an expensive, fixed manufacturing run, and the company said it has not yet had the design fabricated.
Every figure in this account is the company’s own, published without independent replication or third-party verification, in a paper whose sole listed author is Architect Labs itself. The claim follows several years in which AI-assisted design tools have automated specific stages of chip layout — including Google DeepMind’s AlphaChip, in production use for TPU design since 2020. Architect Labs’ claim is broader, covering the full path from specification to a verified design, but unlike AlphaChip’s multi-year record in shipped chips, it has yet to be tested outside the company that built it.