ASML and TSMC launch joint push for 12-inch photomasks to unlock High-NA EUV
The initiative targets a 12-inch mask pilot line by 2031, after TSMC starts using today's smaller 6-inch-mask High-NA systems in advanced-node production from 2030.
- Compute & infrastructure
- Minor
ASML and TSMC announced a joint industry initiative to move the semiconductor industry from 6-inch to 12-inch photomasks for High-NA EUV lithography, the chipmaking technique used to etch the smallest, most advanced transistor patterns. The companies formed the initiative on 7 September, ahead of the annual SPIE BACUS conference in Monterey, California, and set a target of establishing a 12-inch mask pilot line by 2031, with full lithography-system readiness for advanced-node production following in 2033.
A photomask is the template a lithography machine projects onto a silicon wafer to pattern each layer of a chip; ASML said the larger 12-inch format would increase fab productivity, lower chipmaking costs and remove “stitching constraints” — the need to join multiple smaller mask exposures to pattern a single large die, a limitation that becomes more pressing as AI accelerator chips grow larger. High-NA EUV itself will initially reach production using today’s 6-inch masks, with TSMC chairman and chief executive C.C. Wei saying the company intends to use ASML’s High-NA systems in high-volume manufacturing of advanced nodes from 2030, with the number of layers requiring High-NA expected to rise as transistor architectures grow more complex, driven in large part by AI chip demand.
ASML chief executive Christophe Fouquet said the company was “pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative.” The press release names only ASML and TSMC as the initiative’s signatories, describing other “High NA EUV adopters and major suppliers” as having expressed interest in joining; TrendForce’s coverage noted that Samsung and Intel have their own separate High-NA timelines — Samsung targeting first high-volume DRAM production on the technology by 2028, Intel citing more than a million wafers already processed on select layers — but reported those as parallel roadmaps rather than commitments co-signed to this specific 12-inch mask initiative.